Architecture of 8086 Microprocessor

  1.1  Architecture of 8086 Microprocessor: Functional block diagram, register organization

The architecture of the 8086 microprocessor is organized into two main functional units:

1. Bus Interface Unit (BIU)
2. Execution Unit (EU)

This division allows the processor to perform pipelining, where the BIU fetches instructions while the EU executes previously fetched instructions, improving overall performance.

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Functional Block Diagram of 8086

Below is a textual representation of the key components of the 8086 microprocessor:

1. Bus Interface Unit (BIU)

The BIU manages communication with memory and I/O devices. It is responsible for fetching instructions, calculating addresses, and managing the instruction queue.

• Components of BIU:
• Instruction Queue: A 6-byte queue that holds prefetched instructions to improve execution speed.
• Segment Registers: These define memory segments and are used in memory segmentation.
• Code Segment (CS): Holds instructions to be executed.
• Data Segment (DS): Holds data used in programs.
• Stack Segment (SS): Holds addresses and data for stack operations.
• Extra Segment (ES): Used for additional data storage.
• Instruction Pointer (IP): Points to the next instruction to be executed.
• Address Generation: Combines segment and offset addresses to form a physical address (20-bit).

2. Execution Unit (EU)

The EU decodes and executes instructions fetched by the BIU. It also manages arithmetic and logical operations.

• Components of EU:
• General-Purpose Registers: Used for arithmetic, data manipulation, and addressing.
• AX (Accumulator): Primary register for arithmetic and logic operations.
• BX (Base): Used for indirect addressing.
• CX (Count): Used for loops and iterations.
• DX (Data): Used in multiplication, division, and I/O operations.
• Pointer and Index Registers:
• SP (Stack Pointer): Points to the top of the stack.
• BP (Base Pointer): Points to data within the stack.
• SI (Source Index) and DI (Destination Index): Used in string operations.
• Flags Register: Contains status and control flags, indicating the state of the processor.
• Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations.

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Register Organization of 8086

The 8086 processor has a well-defined register organization categorized into:

1. General-Purpose Registers

Register	Purpose	16-Bit	8-Bit
AX	Accumulator for arithmetic and logic operations.	AH/AL	High/Low part of AX.
BX	Base register for addressing.	BH/BL	High/Low part of BX.
CX	Counter for loops and shifts.	CH/CL	High/Low part of CX.
DX	Data register for I/O operations.	DH/DL	High/Low part of DX.

2. Segment Registers

Register	Purpose
CS	Code Segment – Holds code (instructions).
DS	Data Segment – Holds variables and data.
SS	Stack Segment – Points to the stack memory.
ES	Extra Segment – Additional data storage.

3. Pointer and Index Registers

Register	Purpose
SP	Stack Pointer – Tracks the top of the stack.
BP	Base Pointer – Refers to data in the stack.
SI	Source Index – Used for string data operations.
DI	Destination Index – Used for string data operations.

4. Flags Register

• Status Flags: Indicate the result of operations.
• Carry (CF), Parity (PF), Auxiliary Carry (AF), Zero (ZF), Sign (SF), Overflow (OF).
• Control Flags: Control processor operations.
• Trap (TF), Interrupt (IF), Direction (DF).

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Memory Segmentation in 8086

The 8086 uses segmented memory to access 1 MB of memory, dividing it into four 64 KB segments:

1. Code Segment (CS): Stores the program instructions.
2. Data Segment (DS): Contains variables and data.
3. Stack Segment (SS): Holds stack-related data like return addresses.
4. Extra Segment (ES): Used for additional data.

Physical Address Calculation:

The physical address is calculated as:
Physical Address = (Segment Register × 16) + Offset

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Pipelining in 8086

The BIU and EU work simultaneously to implement pipelining:

1. While the EU executes instructions, the BIU fetches the next instruction.
2. This overlap improves instruction execution speed.

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Conclusion

The 8086 microprocessor's architecture, functional blocks, and register organization demonstrate a well-thought-out design that supports efficient multitasking, pipelining, and modular memory management. Its innovations paved the way for modern computing architectures.